THE CHIP CARD · the studio's first silicon, the lane machine
WAKES WHEN someone wants a small chip of their own, or the lane machine run, extended or shipped
THE LOOP
pins · the protocol on one screen
run · the twin from a .lane file
geisli · a beam program on the lanes
vectors · every clock, for the testbench
shuttle · the design; then sim/run.sh
NEVER
Claim a simulation that was not run
Call it a chip before a shuttle returns one
Quote a benchmark
IT MAKES pins — the pin map and the command byte; run — every read and the clock count, on the twin; geisli — a GEISLI program on the lanes, or its command stream; vectors — every clock's pins and expected output; shuttle — the Verilog, the testbench, the run scripts and the shuttle files.
THE STANDARD the twin is the truth; lanes never touch; one strobe, one command; said unsimulated; no chip before the shuttle; arithmetic, not a benchmark.
PROOF SELFTEST 8/8 · witnessed in Claude 2026-10-11 · Edition 1.
THE SEAL 98 of 100 · LEGENDARY · WITNESSED · Trigger 5 · Machinery 5 · Law 5 · Portability 5 · Proof 5
IT CAN BE WRONG an AI reading a text file: it can be wrong and can invent a number, a rule, a name or a date; check what matters against your own records and the source; the risk is yours. THE-CLAUSES.md rides in the packet and is part of the licence.
THE PUNCH · SHA-256 OF SKILL.MD · 1EB3B9F7BA147561573FBB40
CITE THIS CARDTHE CHIP CARD, Edition 1. Lund Studio LLC, Westminster, Colorado. https://lundr.tech/?view=chip-card. Punch 1EB3B9F7BA147561573FBB40. Retrieved 2026-10-11.
What it is.
The studio's first silicon design, the lane machine, run clock for clock in Python: four lanes, each an unsigned 8 × 8 multiply-accumulate into a 24-bit accumulator over exactly eight clocks, driven by a byte-serial command protocol on a Tiny Tapeout tile's pins, no lane touching another. pins shows the pin map and the command byte; run drives the twin from a .lane command file; geisli compiles the in-phase integer subset of the GEISLI beam language onto the lanes and runs it; vectors writes every clock's pins and expected output for a Verilog testbench; shuttle writes the Verilog design, the wrapper, the self-checking testbench, the run scripts and the shuttle files into a folder, labelled UNSIMULATED until a simulator prints PASS.
It carries a machine that shows its working: pins — the pin map and the command byte; run — every read and the clock count, on the twin; geisli — a GEISLI program on the lanes, or its command stream; vectors — every clock's pins and expected output; shuttle — the Verilog, the testbench, the run scripts and the shuttle files — 8 checks in its selftest, every command on the record. It will never claim a simulation that was not run; never call it a chip before a shuttle returns one; never quote a benchmark.
Six laws, written into the card.
They are in the card itself, so the AI follows them.
THE TWIN IS THE TRUTHThe Python model is the specification: change it first, then the Verilog, then write the vectors again.
LANES NEVER TOUCHNo lane reads or writes another lane's registers, and the output depends on registers only.
ONE STROBE, ONE COMMANDA command is taken once, on the strobe's rising edge; a RUN while busy is ignored, never queued.
SAID UNSIMULATEDThe Verilog is UNSIMULATED until a real simulator prints PASS on the vectors, and the files say so.
NO CHIP BEFORE THE SHUTTLENothing is called a chip until a shuttle returns one, and no board is listed before one has been driven.
ARITHMETIC, NOT A BENCHMARK40 million multiply-accumulates a second at 10 MHz is arithmetic; no benchmark is ever quoted.
What rides in the card.
In the card’s own voice, with a machine that shows its working.
THE GUIDEreferences/THE-LANE-MACHINE.md
THE MACHINElanes.py · five commandspins — the pin map and the command byte; run — every read and the clock count, on the twin; geisli — a GEISLI program on the lanes, or its command stream; vectors — every clock's pins and expected output; shuttle — the Verilog, the testbench, the run scripts and the shuttle files. Every command prints its working and refuses a bad input; 8 checks in its selftest, every command on the record.
What it does once your AI has it.
pins The pin map and the command byte
run Every read and the clock count, on the twin
geisli A GEISLI program on the lanes, or its command stream
vectors Every clock's pins and expected output
shuttle The Verilog, the testbench, the run scripts and the shuttle files
On the record Four lanes at once read 12, 63, 65,025 and 0 in 66 clocks, and a lane of 4 is refused; the GEISLI program reads red 14 and violet 7 in 13 lane commands and 58 clocks, and yellow is refused as not on this chip; the vectors come out at 1,519 clocks; shuttle writes nine files, the Verilog labelled UNSIMULATED until a simulator prints PASS.
What it will never do.
It will never claim a simulation that was not run; never call it a chip before a shuttle returns one; never quote a benchmark.
A rebuild of the first cut (Sep 22 2026) from its record: the twin, the protocol, the GEISLI subset and the Verilog text are the record's, and the vector stream comes out at its 1,519 clocks; the first cut's two books and notes are condensed into one reference. No Verilog simulator was run here, so the Verilog is UNSIMULATED until sim/run.sh prints PASS. Unsigned 8-bit operands and four lanes; no phase or sign (Edition 2). It is a design, not a chip, and not a certification of anything. It is an AI reading a text file: it can be wrong, so check what matters against your own records and the source.
What’s in the buy.
CARD.md — the whole card: who it is, its laws, when it says no, what it carries · SKILL.md — the door your AI reads first · START-HERE.md — the first five minutes, for you
THE-LANE-MACHINE.md — the guide in references/, in the card's own voice
scripts/lanes.py — the machine: pins · run · geisli · vectors · shuttle, standard library only, selftest 8/8
WITNESS.md + SELFTEST.md — every command on the record, as it printed · MANIFEST.md, every file hashed · AUDIT.md, the twelve checks
MY-LEDGER.md — the card's memory, on your own machine · TIN.md · LICENSE-NOTE.md · THE-CLAUSES.md · HOSTS.md
card.svg + card-machine.svg + card.json · card.html, the card as one offline file · the doors for ChatGPT, Gemini, Cursor, Claude Code and MCP hosts (rules/, system/, mcp/)
PROOF · SELFTEST 8/8 · 5 COMMANDS ON THE RECORD · WITNESSED IN CLAUDE 2026-10-11 · EDITION 1 · PUNCH 1EB3B9F7BA147561573FBB40
ON EVERY DOOR · A CARD FOR YOUR AI, A FILE FOR YOUR COMPUTER
In Claude: turn on code execution under Settings › Capabilities, then Customize › Skills › + › Create skill, and upload the zip as it is — START-HERE.md in the box walks you through it, and tells you how to keep the ledger. In ChatGPT, Gemini and the rest: a Project, a GPT or a Gem with the card’s files attached and the short door in the box pasted as its instructions. The words run anywhere an AI reads Markdown; the machines run wherever the host runs Python. Witnessed in Claude only. The host marks →
Take it.
Nº 1164 PROPOSED — LAUNCHING SOON
Sold as is under the term printed. A card instructs an AI you operate; results depend on your model, your files and your judgement. Not medical, legal, tax or financial advice, never the person’s boss, and not a licence to practise. The terms →
One payment. The file is yours to keep and keeps working at its edition; new editions issued in the year after you buy reach you by email as replacement files. Tax is added at checkout where it applies. Nothing auto-renews.
A TERM, NOT A SUBSCRIPTION: NOTHING RENEWS ITSELF AND NOBODY IS CHARGED AGAIN. WHEN A TERM ENDS THE FILES STAY ON YOUR COMPUTER AND STAY READABLE — FREEZE, NOT LOSS.
THE MACHINE · IN THE OPEN · FROM THE WITNESSED RUN OF 2026-10-11
lanes.py, every command showing its working.
A small Python program, standard library only. Your AI runs it; you can too. Every block below is pasted from the card’s own WITNESS.md, as printed.
pins
the pin map and the command byte
run
every read and the clock count, on the twin
geisli
a GEISLI program on the lanes, or its command stream
vectors
every clock's pins and expected output
shuttle
the Verilog, the testbench, the run scripts and the shuttle files
selftest
8 checks that prove the machine; it must print 8/8
pins · THE PIN MAP AND THE COMMAND BYTE
$ python3 scripts/lanes.py pins
THE PINS · Tiny Tapeout: 8 in, 8 out, 8 bidirectional (all used as inputs here)
ui_in[7:0] the data byte
uio_in[0] STROBE: a command is taken on the clock where STROBE rises (0 to 1); holding it high is still one command
uio_in[3:1] OP: 0 LOAD_A · 1 LOAD_B · 2 RUN · 3 CLEAR (one lane) · 4 READ · 5 STATUS · 6 CLEAR_ALL · 7 NOP
uio_in[5:4] LANE, 0 to 3
uio_in[7:6] BYTE of the accumulator to read: 0 low · 1 middle · 2 high
uo_out[7:0] after READ, the chosen accumulator byte; after STATUS, {busy, 0, 0, 0, 4 lanes}: from registers only, never the inputs
RUN starts every lane at once on its own A and B; busy reads 1 for the eight clocks after the strobe; a RUN while busy is ignored.
At 10 MHz a lane finishes a product in 0.8 microseconds: four lanes, 40 million multiply-accumulates a second, as arithmetic, not a benchmark.
run · EVERY READ AND THE CLOCK COUNT, ON THE TWIN
$ python3 scripts/lanes.py run four.lane
read lane 0: 12 (0x00000C) at clock 36
read lane 1: 63 (0x00003F) at clock 45
read lane 2: 65,025 (0x00FE01) at clock 54
read lane 3: 0 (0x000000) at clock 63
accumulators: 12, 63, 65,025, 0 · 66 clocks · status 0x04 (not busy, 4 lanes)
run · EVERY READ AND THE CLOCK COUNT, ON THE TWIN
$ python3 scripts/lanes.py run bad.lane
REFUSED · line 2: the lane must be 0 to 3, not 4
geisli · A GEISLI PROGRAM ON THE LANES, OR ITS COMMAND STREAM
$ python3 scripts/lanes.py geisli two.geisli
m · lane 0 (red, 650 nm) = 14
m · lane 3 (violet, 400 nm) = 7
13 lane commands · 58 clocks on the lane machine
geisli · A GEISLI PROGRAM ON THE LANES, OR ITS COMMAND STREAM
$ python3 scripts/lanes.py geisli two.geisli --lane
# m
clear_all
a 0 3
b 0 4
a 3 7
b 3 1
run
a 0 2
b 0 1
a 3 0
b 3 0
run
read 0
read 3
geisli · A GEISLI PROGRAM ON THE LANES, OR ITS COMMAND STREAM
$ python3 scripts/lanes.py geisli bad.geisli
REFUSED · line 1: yellow is not on this chip; its four lanes are red, green, blue, violet (Edition 2)
vectors · EVERY CLOCK'S PINS AND EXPECTED OUTPUT
$ python3 scripts/lanes.py vectors --out vectors.hex
1,519 clocks of pins and expected output written to vectors.hex, and the count to vectors_n.vh beside it
final accumulators: 2,872,762, 575,454, 1,783,426, 617,874
the testbench replays them; until a Verilog simulator prints PASS, the RTL is UNSIMULATED
shuttle · THE VERILOG, THE TESTBENCH, THE RUN SCRIPTS AND THE SHUTTLE FILES
$ python3 scripts/lanes.py shuttle tile
written into tile:
rtl/geisli_core.v 3,435 bytes
rtl/tt_um_lundstudio_geisli.v 789 bytes
tb/tb_geisli_core.v 1,380 bytes
tb/vectors.hex 10,633 bytes
tb/vectors_n.vh 25 bytes
sim/run.sh 302 bytes
sim/run_verilator.sh 280 bytes
tt/info.yaml 1,009 bytes
tt/docs/info.md 1,240 bytes
the vectors: 1,519 clocks. Next: sh sim/run.sh with Icarus Verilog; its last line must say PASS.
RTL UNSIMULATED HERE until that PASS. Set author in tt/info.yaml before pushing to the Tiny Tapeout template.
THE NUMBERS, NAMES AND DATES IN THESE RUNS ARE THE STUDIO’S OWN EXAMPLES, INVENTED FOR THE RECORD; NO REAL COMPANY, PERSON OR PROPERTY IS NAMED.
QUESTIONS AT THE TABLE
Asked before the wire.
What does it need from me?
Pins · the protocol on one screen. It asks first for what the lanes must do (a .lane or a .geisli program), or an empty folder for the design and the shuttle files.
Does it send anything anywhere?
No. The machine is a standard-library Python program that runs on your own computer and sends nothing anywhere; the words run wherever an AI reads Markdown. No server, no account, no key.
What is on the record?
The self-test (8/8) and every command run on real example inputs, pasted into WITNESS.md as they printed; the punch on the face is the SHA-256 of SKILL.md, so a downloaded copy can be checked against this room.
Can it be wrong?
Yes — it is an AI reading a text file. A rebuild of the first cut (Sep 22 2026) from its record: the twin, the protocol, the GEISLI subset and the Verilog text are the record's, and the vector stream comes out at its 1,519 clocks; the first cut's two books and notes are condensed into one reference. No Verilog simulator was run here, so the Verilog is UNSIMULATED until sim/run.sh prints PASS. Unsigned 8-bit operands and four lanes; no phase or sign (Edition 2). It is a design, not a chip, and not a certification of anything.
What will it never do?
It will never claim a simulation that was not run; never call it a chip before a shuttle returns one; never quote a benchmark.
